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TM
PRELIMINARY
May 1999
T NT DUC PRO LACEME 747 TE OLE REP 00-442-7 OBS ENDED -8 M ns 1 l.com COM pplicatio Intersi RE @ NO ntral A app e cent all C email: C or
HFA3665
Description
CDMA/AMPS Downconverter with AGC Capability
Features
* RF Frequency Range . . . . . . . . . . . . 869MHz to 895MHz * IF Operation . . . . . . . . . . . . . . . . . . . . 10MHz to 100MHz * LNA Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16dB * LNA NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3dB * Mixer Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16dB * Mixer NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11dB * Single Supply Battery Operation . . . . . . . . 2.7V to 3.3V * Power Enable/Disable Control * PIN Diode Attenuator DC Control
Applications
* IS95A CDMA/AMPS Dual Mode Handsets * Wideband CDMA Handsets * CDMA/TDMA Packet Protocol Radios * Full Duplex Transceivers * Portable Battery Powered Equipment
The HFA3665 is a monolithic bipolar downconverter for CDMA/AMPS cellular applications. Manufactured in the Intersil UHF1X process, the device consists of a low noise cascode amplifier, a double balanced downconversion mixer and a pair of linearized and temperature compensated PIN diode biasing current sources for external RF AGC applications. In addition, the device offers two independent and selectable differential mixer IF output ports to be used with dual mode IF filters and requires low drive levels from the local oscillator. The HFA3665 is one of the four chips in the PRISMTM chip set and is housed in a small outline 28 lead SSOP package ideally suited for cellular handset applications.
Ordering Information
PART NUMBER HFA3665IA HFA3665IA96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 28 Ld SSOP Tape and Reel PKG. NO. M28.15
Pinout
HFA3665 (SSOP) TOP VIEW
VCC 1 AGC_CTRL 2 PIN_O_IBIAS1 3 GND 4 LNA_OUT 5 LNA_OUT 6 GND 7 GND 8 LNA_IN 9 PIN_O_IBIAS2 10 PIN_I_GND 11 RX_PE 12 R_REF 13 BIAS_GND 14 28 MIX_VCC 27 SEL 26 MIX_VCC 25 MIX_IND 24 RF_IN 23 RF_RET 22 MIX_GND 21 LO_RET 20 LO_IN 19 CDMA_OUT18 CDMA_OUT+ 17 FM_OUT16 FM_OUT+ 15 BIAS_VCC
Block Diagram
LNA_OUT RF_IN CDMA_OUTLNA_IN LNA CDMA_OUT+ PIN_O_IBIAS1 C T R L BIAS FM_OUT+ RX_PE AGC_CTRL LO_IN SW SEL FM_OUT-
PIN_O_IBIAS2
PRISMTM and the PRISMTM logo are trademarks of Intersil Corporation.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Intersil Corporation 1999
File Number
4301.5
1
HFA3665 Pin Descriptions
PIN NUMBER 1 NAME VCC AGC_CTRL DESCRIPTION LNA and PIN diode bias control Power Supply.Use high quality RF decoupling capacitors at the pin. AGC control current input pin. Requires a 9.53K 1% resistor for scale factor and temperature compensation of the current sources. Current output for a PIN diode bias control. Use a 2200pF filter capacitor to ground. LNA bias ground return. LNA open collector output. This pins are internally bonded to the same device output. LNA RF ground return. Degeneration (inductance) can be added to this pin. LNA input. Second current output for PIN diode bias control. Use a 2200pF filter capacitor to ground. PIN diode bias control ground return. Power enable control input. HIGH for normal operation. LOW for power down. Bias setting resistor. 523 1% for optimum performance and parameter distribution. Reference circuit ground return. Reference circuit Power Supply. Use high quality RF decoupling capacitors right at the pin. Positive IF FM output. Open collector PNP. Requires a DC return to ground. Negative IF FM output. Open collector PNP. Requires a DC return to ground. Positive IF CDMA output. Open collector PNP. Requires a DC return to ground. Negative IF CDMA output. Open collector PNP. Requires a DC return to ground. Mixer Local Oscillator input. Requires AC coupling and directly matches to 50. Mixer Local Oscillator complementary input. Requires a bypass capacitor to ground as a return reference. Mixer ground return. MIxer RF port complementary input. Requires a bypass capacitor to ground as a return reference. Mixer RF input. Requires AC coupling and a match network to 50. Mixer common mode bias inductor. Use a RF choke to ground with high impedance at 900MHz. Low loss inductors with parallel resonance close to 900MHz are ideal. Mixer Power Supply Pins.Use high quality RF decoupling capacitors at each one of the pins. Selects the CDMA or the FM output IF amplifier. HIGH selects the CDMA amplifier. LOW the FM amplifier output.
2
3 4 5, 6 7, 8 9 10 11 12 13 14 15 16 17 18 19 20 21
PIN_O_IBIAS1 GND LNA_OUT GND LNA_IN PIN_O_IBIAS2 PIN_I_GND RX_PE R_REF BIAS_GND BIAS_VCC FM_OUT+ FM_OUTCDMA_OUT+ CDMA_OUTLO_IN LO_RET
22 23
MIX_GND RF_RET
24 25
RF_IN MIX_IND
26, 28
MIX_VCC SEL
27
2
HFA3665
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 3.6V Voltage on Any Other Pin except 5 and 6 (6.0V) . -0.3 to VCC +0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Temperature Range . . . . . . . . . . . . . . -40oC TA 85oC Maximum Storage Temperature Range . . . . . ..-65oC TA 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 3.3V Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40oC TA 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(NOTE 2) TEST LEVEL TEMP (oC)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
LNA SPECIFICATIONS AT 885MHz, VCC = 3.0V,VLNA = 3.0V unless otherwise specified (Test schematics as in page 5) RF Frequency Range Power Gain IP3I, Input referenced 3rd Order Intercept Output Match net. -30dBm input VLNA = 3.0V VLNA = 3.6V VLNA = 5.0V IP1dB, Input Referenced Compression Point VLNA = 3.6V Noise Figure Input VSWR Output VSWR Output network as in the Apps. diagram B A A A A A B A A 25 25 25 25 25 25 25 25 25 869 14 16.0 +2 +6 +7.5 -7 2.3 2.2:1 1.6:1 895 17.5 2.5:1 2.0:1 MHz dB dBm dBm dBm dBm dB -
MIXER SPECIFICATIONS AT -3dBm LO at 970MHz AND IF of 85MHz RF Frequency Range (Typical) IF Frequency Range LO Frequency Range (Typical) Power Conversion Gain Voltage Conversion Gain Note 3 Differential IF output load = 2.95K B B B A B 25 25 25 25 25 869 10 954 15.1 85 16.7 34.4 895 100 980 18.3 MHz MHz MHz dB dB
Gain Flatness Across the RF Freq. Range Noise Figure, SSB IP3I, Input Referenced 3rd Order Intercept IP1dB, Input Referenced Compression Point LO Drive Level LO to IF Isolation LO to RF Isolation RF VSWR Input network as in the Apps diagram Note 3
B B A A A A A A
25 25 25 25 25 25 25 25
0 -6 20 -
10.6 2.6 -10 -3 30 32 1.6:1
0.6 11.4 0 2:1
dB dB dBm dBm dBm
dB -
3
HFA3665
Electrical Specifications
(Continued) (NOTE 2) TEST LEVEL A B
PARAMETER LO VSWR IF Output Parallel Resistance CDMA or FM port (85MHz) Single End to GND. IF Output Parallel Capacitance CDMA or FM port (85MHz) Single End to GND.
TEST CONDITION
TEMP (oC) 25 25
MIN -
TYP 2.0:1 12.4
MAX -
UNITS k
B
25
-
1.7
-
pF
PIN DIODE BIAS CURRENT SOURCE SPECIFICATIONS (EACH OUTPUT Terminated into 0.7V) Typical PIN diode AGC Range
AGC_CTRL Voltage control Range
Application schematic. Rseries = 9.53K AGC_CTRL = 2.0V AGC_CTRL = 1.8 AGC_CTRL = 1.4V AGC_CTRL = 1.0V
B A A A A A A B B
Full 25 25 25 25 25 25 25 25
33 0.5 -
38 5.2 3.0 0.47 0.04 0.0 200 330
2.5 -
dB V mA mA mA mA mA A/oC A/V
PIN_O_IBIAS Max. Source Current. PIN_O_IBIAS Current
PIN_O_BIAS Leakage current PIN_O_IBIAS Current Vs Temperature PIN_O_IBIAS Current Vs Supply Voltage
AGC_CTRL = 0.5V AGC_CTRL = 1.8V AGC_CTRL = 1.8V
POWER SUPPLY AND LOGIC SPECIFICATIONS Supply Voltage LNA Power supply (VLNA) SEL And RX_PE,VIL SEL And RX_PE,VIH SEL AND RX_PE, Input Bias Currents at VCC VIH = 3.0V = 3.0V VIL = 0.0V LNA/Mixer Supply Current Total PIN Diode Bias Circuit Supply Current Power Down Supply Current Power Down Speed NOTES: 2. A = Production Tested, B = Based on Characterization, C = By Design 3. Output differential to single end match network to 50 for both CDMA and FM IF ports (Production Test Diagram in page 5). AGC_CTRL = 0.5V AGC_CTRL = 1.8V RX_PE = Low B C A A A A A B A B 25 25 25 25 25 25 25 25 25 25 2.7 2.7 2.0 -200 -200 45 11 10 3.3 5.5 0.8 +200 +200 100 10 V V V V A A mA mA A s
4
HFA3665 Production Test Diagram
MIXER RF IN
50
VCC
220p
220p 0.1
1 AGC
9.53k 47p C1 2200p
VCC
MIX_VCC
47p
2 3
AGC_CTRL
SEL
SEL
PIN_O_IBIAS1 MIX_V CC 18n MIX_IND RF_IN 100p ? 4.7p 15n RF_RET LNA_GND MIX_GND LNA_OUT 15p 220p 0.1
PIN BIAS 1
C3
4
1.5p
GND LNA_OUT
LNA OUT
50
VLNA
8.2n
5 6
R9 100p NOTE 4
RF_LO_INPUT
50
7 8
LO_RET LO_IN CDMA_OUT-
12p
LNA IN
100p
50
9
LNA_IN
100p 6.6K
220nH 7.5p 220nH
10 PIN_O_IBIAS2 PIN BIAS 2
2200p
11 PIN_I_GND
0.01
12 RX_PE PE 13 R_REF
CDMA_OUT+ FM_OUT12p
330nH
CDMA IF OUTPUT 50
HFA3665
523 1%
FM_OUT+
BIAS_ CC V
14 BIAS_GND
220nH 6.6K 0.33 7.5p 220nH
100p 330nH 12p
FM IF OUTPUT
50
NOTE: 4. PC trace degeneration inductor. 93mil by 8mil trace terminating in a 10mil via. Via is tied to a buried solid ground plane 12mils deep. Material is FR4 Er = 4.7.
5
Typical RF Front End AGC Application Diagram
S+M B4691
8.2n L11 4p C1 4p C7
R3 R4 12 12p C2
12
82n L1
VCC
PIN
220p
220p
0.33 47p
AGC
R1 9.53k
1
47p C1
VCC
AGC_CTRL
MIX_VCC
2 3 4
SEL
C7
2200p 49.9k C3 C13 1.5p L2 100p 8.2n LE NOTE 5 100p C5 C4 13p 82n L4 C6 49.9K R5 R2
SEL
PIN_O_IBIAS1
MIX_VCC
L5 18n 100p ? C9
220p
0.1
GND LNA_OUT
MIX_IND 4.7p C8 15n L6 MIX_GND RF_IN
5 6 7 8 9
VLNA
Note 1
LNA_OUT LNA_GND
RF_RET
15p
RF_LO_INPUT
LO_RET LO_IN
12p
SAWTEK 855292 270n
LNA_IN
10 PIN_O_IBIAS2 11 PIN_I_GND
0.01
CDMA_OUT-
100p 6.2K R7
L7
PIN
2200p
L8 CDMA_OUT+ FM_OUT270n
C10 25.3p
12 RX_PE PE FROM PA
523 1% R6
13 R_REF
FM_OUT+
BIAS_VCC
14 BIAS_GND
6.6p C12 0.33
L10
100p 390n 5p C11 330n MURATA SX439A
PIN DIODE: MACOM MA4P282-1141 DUPLEXER: DFY2RR836CR881BHHN
NOTE: 5. LNA degeneration inductance built with a PC trace to ground in combination with VLNA power supply to improve IIP3. A transmission line inductance of 1.2nH at 882MHz to a solid ground plane is typical (see Test Diagram).
6
FM OUTPUT
HFA3665
L9 R8 6.2K
CDMA OUTPUT
25.3p C9
HFA3665
DESIGN INFORMATION
External AGC Application Components Description
(Please refer to Typical RF and Front End AGC Application Diagram)
NOTE:In order to avoid input insertion losses and maintain the Noise Figure of this application optimized, the VSWR of the LNA input attenuator scheme is directly impacted by the input shunt PIN diode impedance when AGC is in action. This mismatch is absorbed by the duplexer/filter and there is no significant impact in its duplex characteristics to both antenna and transmitter ports.
LE adds degeneration to the LNA input for higher input intercept points. This combination of degeneration and a higher LNA VCC (VLNA) improves considerably the input intercept point with a slight decrease in gain. LE shall have very high Q and can be build with a small PC trace. L1 and L4 permit DC biasing of the PIN diodes and RF isolation. Several types of 82nH inductors have SRF near 900MHz thus maximizing the RF isolation. L2 and C13 are part of the output matching network and provides the DC bias path for the open collector output. R7 and R8 define the Real part of the CDMA and FM output ports impedances. Unloaded "Q" of the coils used for proper biasing of these ports have to be taken into account when defining these values. The total load presented to these ports also define the achievable gain of the mixers. Because there is no internal feedback between the complementary ports of the differential channel, the loads and ports can be split into independent ports referenced to ground. L7, L8 and L9, L10 have two functions: They provide a DC path to ground required for proper operation of the CDMA and FM differential outputs and can also be part of the match network between these ports and IF filters. C9, C10 and C12 are part of a match network to the suggested filters. L9, L10 and C12 are part of a current summer network for a differential to single end conversion. L12, L13 and C11 form a high "Q" match network between the converter and the suggested filter for the SAW IP3 distortion optimization. All other unlabeled components on the schematics are bypass/decoupling capacitors. Values are chosen based on their SRF.
R3 and R4 limit the output attenuation range and output VSWR. R1 sets the scale factor, temperature coefficient and range of the gain control voltage. R2 sets the turn-on point for the output PIN diode attenuator and R5 sets the turn-on point for the input PIN diode attenuator by shunting to ground some of the PIN diode bias current. By making R5 a smaller value than R2, the output attenuator turns on first, to optimize NF. Making R5 = R2 will turn both PIN diodes simultaneously to optimize the IIP3 during the initial AGC action. The R2/R5 combination can be tailored to specific AGC characteristics. R6 generates the reference current which is used to set the operating point of all the major RF and IF transistors. A proportional to temperature (PTAT) voltage of about 37mVat25oC is applied to this resistor. PTAT biasing keeps the gain temperature independent. A 10% variation from 523 is allowed. Lower values increase the total LNA and Mixer bias currents. C1 filters noise from the gain control source to reduce unwanted AM modulation. C2 and C4 provide DC isolation for PIN diode biasing. Their values are chosen to provide series resonance cancelling of the diode package and PC board inductances. C3 and C6 decouple the PIN diode bias pins. Failure to decouple these pins may cause LNA oscillations.
7
HFA3665 Shrink Small Outline Plastic Packages (SSOP)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45o L GAUGE PLANE H 0.25(0.010) M BM
M28.15
28 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8o Rev. 0 2/95
A1 0.10(0.004) A2 C
E e H h L
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.228 0.0099 0.016 28 0o 8o 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 28 0o 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
N
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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